Carbon nanotubes grown on silicon wafers go in all directions (right), whilenanotubes grown on crystalline quartz are much more orderly, mostly growingin straight rows (left).
Image: Stanford University Department of Electrical Engineering
Carbon nanotubes have been around for more than a decade, but so far they haven’t shown up anywhere outside of R&D labs and tennis racquets.
Now, two separate groups of researchers have recently published papers demonstrating advances in creating, sorting and organizing carbon nanotubes so they can be used in electronics.
Because they are so small and could potentially replace two of the basic components of modern microchips (conductors and semiconductors), nanotubes have continued to pique the interest of electronics researchers. And that interest continues to grow, especially as the current technology used to make chips for electronics begins to reach its physical limits.
The trouble is that, until recently, making nanotubes was a somewhat random affair: You’d mix the required ingredients, grow a batch of nanotubes, and then sort through the resulting batch to see what you got. Researchers had no effective way to grow exclusively metallic or exclusively semiconducting nanotubes, and even ordering the nanotubes in regular patterns was a challenge. That has made using nanotubes on an industrial scale impractical to the point of impossibility.
“An ant is incredibly strong for its size. But nobody uses ants to do useful work, because they all run around in different directions,” says Mike Mayberry, the director of components research for Intel. (Mayberry was not involved in the research.)
And so nanotubes have grown for the past 15 years — knotty and bent — since the single-walled variety were discovered in 1993 by IBM researcher Donald S. Bethune and NEC researcher Sumio Ijima. As molecular oddities, carbon nanotubes have always been fascinating. Each nanotube is made of a “sheet” of interlocked carbon atoms, rolled up into a single- or multi-walled cylinder. Although each cylinder is a single, narrow molecule no more than a nanometer (nm) or two in diameter, the molecules can grow up to several centimeters in length — or 30 million times their width. A human hair that long would stretch 1.5 miles.
Even better, these strange carbon molecules exhibit great physical strength because they’re held together by atomic bonds. They’ve also got unusual electrical properties: Depending on which way the sheets of carbon are rolled up, nanotubes are either metallic, making them good electrical conductors, or semiconducting, making them potentially useful components for the logic components of microchips.
A paper — presented last month at the VLSI Symposium by Nishant Patil, Albert Lin, Edward R. Myers, H.-S. Philip Wong and Subhasish Mitra, all of Stanford’s electrical engineering department — addresses the problem of getting the nanotubes straightened out so they could be put to work in chips.
To be useful in large-scale chip manufacturing, nanotube components will have to be integrated with existing silicon-based chips. Unfortunately, growing nanotubes on silicon wafers produce a disorderly mess. The authors tackled that problem by growing the nanotubes on crystalline quartz, where they grow in orderly rows, then transferring them to a silicon wafer.
“If you grow carbon nanotubes on silicon, you will see that the carbon nanotubes are really unruly, like a bowl of thin rice noodles,” says Mitra. “If you use a quartz wafer, the nanotubes are largely aligned with each other. They still have kinks and bends and so on, but they’re pretty good.”
Even if the nanotubes are reasonably straight, the problem of selectively creating semiconducting and metallic carbon nanotubes remains. Another paper, published last week in Science by Stanford and Samsung chemical engineers Melburne C. LeMieux, Mark Roberts, Soumendra Barman, Yong Wan Jin, Jong Min Kim and Zhenan Bao, reports that by changing the substrate on which the nanotubes are grown, manufacturers can control what kind of nanotubes form. Using a substrate of aminosilanes, the resulting nanotubes were almost entirely semiconducting, while substrates of aromatic compounds (such as phenyls) produced metallic nanotubes.
That’s a more effective way of getting the right kind of nanotube than previous techniques, which involved sorting nanotubes after they are made using electrical or magnetic fields — and which weren’t usable on a commercial scale.
Nanotubes might be coming on the scene just in time, as modern chipmaking technologies approach their physical limits. Current cutting-edge chip technology creates circuit elements that are 45nm wide, and the next-generation technology, expected in prototype form later this year, will be 32nm. (Smaller circuits are faster and also allow chipmakers to pack more components into a single chip, making processors more powerful and capable.) That’s getting pretty close to the limit of current technologies for two reasons: leakage and light.
As silicon-and-copper circuits get smaller, electricity leakage and heat dissipation become proportionally greater problems than they are with larger circuits. By contrast, a nanotube circuit could potentially be as small as 1 or 2nm, and it would be extremely efficient, even over comparatively long distances.
Also, the photolithography techniques used to etch microchip circuits are running into a physical barrier: The components are smaller than the wavelengths of the light used to etch them. Going smaller will require a completely different technology.
“Lithography is running out of steam,” notes Subhasish Mitra, a co-author of one of the nanotube papers.
While industry researchers welcomed the new papers, they cautioned that it will be quite awhile before nanotubes are used inside microchips.
“These techniques and others are all steps in the right direction. They’re good progress along the way,” says Mayberry.
In the meantime, however, nanotubes might find applications on a larger scale than the inside of a chip. For instance, Mayberry notes that Intel has done research into using nanotube-based wiring as the interconnecting wires between different sections of microchips, or even as part of a chip package’s cooling system.
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